r03ds0038ej0500 rev.5.00 page 1 of 9 jun 03, 2011 preliminary datasheet m62333p/fp, m62338p/fp 8-bit 3ch i 2 c bus d/a converter with buffer amplifiers description the m62333/m62338 is an integrated circuit semiconductor of cmos structure with 3 channels of built in d/a converters with output buff er operational amplifiers. the input is 2-wires serial method is used for the tran sfer format of digital data to allow connection with a microcomputer with minimum wiring. the output buffer operational amplifier employs ab class output circuit with sync and source drive capacity of 1.0 ma or more, and it operates in the whole voltage range from v cc to ground. the m62333 and the m62338 differ only in their slave address. features ? digital data transfer format: i 2 c bus serial data method ? output buffer operational amplifier: it operates in the whole voltage range from v cc to ground. ? high output current drive capacity: ? 1.0 ma over application conversion from digital data to analog control data for home-use and industrial equipment. signal gain control or automatic adjustment of display-monitor or ctv. block diagram a o2 2 3 a o3 8 8 7 6 5 v cc gnd scl sda +? +? 8-bit latch 8-bit latch 8-bit upper segment r-2r a o1 1 +? 8-bit latch 8-bit upper segment r-2r 8-bit upper segment r-2r i 2 c bus transceiver power on reset channel decoder r03ds0038ej0500 rev.5.00 jun 03, 2011
m62333p/fp, m62338p/fp preliminary r03ds0038ej0500 rev.5.00 page 2 of 9 jun 03, 2011 pin arrangement 8 5 6 7 1 4 3 2 m62333p/fp m62338p (top view) a o1 v cc a o2 scl a o3 sda nc gnd nc: no connection outline: prdp0008aa-a (8p4) [p] (not recommend for new design) prsp0008de-c [fp] (recommend) prsp0008da-a (8p2s-a) [fp] (not recommend for new design) 8 5 6 7 1 4 3 2 m62338fp (top view) a o1 v cc a o2 scl a o3 sda nc gnd nc: no connection outline: prsp0008da-a (8p2s-a) pin description pin no. pin name function 6 sda serial data input terminal 7 scl serial clock input terminal 1 a o1 2 a o2 3 a o3 8-bit resolution d/a converter output terminal 8 v cc power supply terminal 5 gnd gnd terminal
m62333p/fp, m62338p/fp preliminary r03ds0038ej0500 rev.5.00 page 3 of 9 jun 03, 2011 absolute maximum ratings item symbol ratings unit supply voltage v cc ?0.3 to 7.0 v input voltage vin ?0.3 to v cc + 0.3 v output voltage v o ?0.3 to v cc + 0.3 v power dissipation pd 417 (p) / 272 (fp) mw operating temperature topr ?20 to 85 ? c storage temperature tstg ?40 to 125 ? c electrical characteristics (v cc = +5 v ? 10%, gnd = 0 v, ta = ?20 to 85c unless otherwise noted) limits item symbol min typ max unit test conditions supply voltage v cc 2.7 5.0 5.5 v 0 0.9 2.7 ma clk = 500 khz operation, i ao = 0 ? a data: 6ah (at maximum current) supply current i cc 0 0.6 1.8 ma sda = scl = gnd, i ao = 0 ? a output low voltage (sda) v ol ? ? 0.4 v isink = 3 ma input leak current i ilk ?10 ? 10 ? av in = 0 to v cc input low voltage v il ? ? 0.2 v cc v input high voltage v ih 0.8 v cc ? ? v 0.1 ? v cc ? 0.1 v i ao = ? 100 ? a buffer amplifier output voltage range v ao 0.2 ? v cc ? 0.2 v i ao = ? 500 ? a buffer amplifier output drive range i ao ?1.0 ? 1.0 ma upper side saturation voltage = 0.3 v lower side saturation voltage = 0.2 v differential nonlinearity s dl ?1.0 ? 1.0 lsb nonlinearity s l ?1.5 ? 1.5 lsb zero code error s zero ?2.0 ? 2.0 lsb full scale error s full ?2.0 ? 2.0 lsb v cc = 5.12 v (20 mv/lsb) without load (i ao = 0) output capacitate load c o ? ? 0.1 ? f buffer amplifier output impedance r o ? 5.0 ? ?
m62333p/fp, m62338p/fp preliminary r03ds0038ej0500 rev.5.00 page 4 of 9 jun 03, 2011 i 2 c bus line characteristics item symbol min max unit scl clock frequency t scl 0 100 khz time the bus must be free before a new transmission can start t buf 4.7 ? ? s hold time start condition (after this period, the first clock pulse is generated) t hd:sta 4.0 ? ? s low period of the clock t low 4.7 ? ? s high period of the clock t high 4.0 ? ? s set-up time for start condition (only relevant for a repeated start condition) t su:sta 4.7 ? ? s hold time data t hd:dat 0 ? ? s set-up time data t su:dat 250 ? ns rise time of both sda and scl lines t r ? 1000 ns fall time of both sda and scl lines t f ? 300 ns set-up time for stop condition t su:sto 4.0 ? ? s note: transmitter must internally provide at least a hold time to bridge the undefined region (300 ns max) of the falling edge of scl. timing chart v ih t buf t su:sto t su:sta t hd:dat t su:dat t hd:sta start start start stop t high t low t r , t f v il sda v ih v il scl
m62333p/fp, m62338p/fp preliminary r03ds0038ej0500 rev.5.00 page 5 of 9 jun 03, 2011 i 2 c bus format sta slave address w a sub address a dac data a stp note: sta: start condition, a: affirmation bi t, w: write (sda = low), stp: stop condition ? slave address 1001111 first last 1001110 first last m62333 m62338 ? sub address channel select data s1 s0 channel selection 0 0 ch1 selection 0 1 ch2 selection 1 0 ch3 selection xxxxxxs1 first last s0 don't care channel select data 1 1 don?t care ? dac data first msb first msb last lsb 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 0 :::::::: : 1 1 0 0 0 0 1 1 0 0 0 0 1 1 00000 00001 00010 00011 1 1 1 1 1 1 1 1 0 1 d7 d1 d6 d5 d4 d3 d2 d0 last lsb dac output v cc / 256 1 v cc / 256 2 v cc / 256 3 v cc / 256 4 v cc / 256 255 v cc
m62333p/fp, m62338p/fp preliminary r03ds0038ej0500 rev.5.00 page 6 of 9 jun 03, 2011 timing chart (model) 12345678a sda scl d/a output sda scl d/a output 1234567 1234567 w a sda scl 8 a d/a output start condition stop condition ? start condition with scl at high, sda line goes from high to low ? stop condition with scl at high, sda line goes from low to high (under normal circumstances, sda is changed when scl is low) ? acknowledge bit the receiving ic has to pull down sda line whenever receive slave data. (the transmitting ic releases the sd a line just then transmit 8-bit data.) digital data formats sta slave address w a sub address 2 a dac data 2 a stp sub address 1 a dac data 1 a sub address n a dac data n a
m62333p/fp, m62338p/fp preliminary r03ds0038ej0500 rev.5.00 page 7 of 9 jun 03, 2011 precaution for use ? supply voltage terminal (v cc ) is also used for d/a converter upper refere nce voltage setting. if ripple or spike is input this terminal, accuracy of d/a conversion is down. so, when use this device, please connect capacitor among v cc to gnd for stable d/a conversion. ? this ic?s output amplifier has an advantage to capacitive load. so it?s no problem at device action when connect capacitor (0.1 ? f max) among output to gnd for every noise eliminate. ? purchase of renesas?s i 2 c components conveys a license under the philips i 2 c patent rights to use these components an i 2 c system, provided that the system conforms to i 2 c standard specification as defined by philips. application example a o1 1 2 4 8 v cc 10 f 5 v 5 v 7 scl 6 sda mcu 5 gnd a o2 a o3 a o1 + a nalog output terminals 3
m62333p/fp, m62338p/fp preliminary r03ds0038ej0500 rev.5.00 page 8 of 9 jun 03, 2011 package dimensions include trim offset. dimension "*3" does not note) do not include mold flash. dimensions "*1" and "*2" 1. 2. seating plane 85 4 1 *1 *2 *3 *3 e 1 c d e e b 2 b 3 b p la a 1 a 2 2.79 2.29 4.5 a 1 b 3 15 e 2.54 c l 3.0 0.51 1.4 1.5 1.8 a e 6.15 6.3 6.45 d 8.7 8.9 9.1 reference symbol dimension in millimeters min nom max 0.22 0.27 0.34 p-dip8-6.3x8.84-2.54 0.5g mass[typ.] 8p4 prdp0008aa-a renesas code jeita package code previous code b p 0.4 0.5 0.6 e 1 7.62 7.32 7.92 b 2 0.9 1.0 1.3 a 2 3.3 0 a l e c 1 b 1 d e a 2 b p c x y h e z l 1 4.85 4.65 0.90 0.12 0 8 6.2 0.15 0.20 0.25 1.12 1.42 0.46 0.00 0.1 0.20 4.4 1.85 4.6 4.2 0.25 0.45 0.65 2.03 reference symbol dimension in millimeters min nom max 5.05 a 1 0.34 0.4 6.5 5.7 1.27 0.10 0.75 5 8 4 f *1 *2 *3 p m x y 1 index mark e a z b e h d p terminal cross section ( ni/pd/au plating ) c b 1 detail f a 2 a note) 1. dimensions"*1 (nom)"and"*2" do not include mold flash. 2. dimension"*3"does not include trim offset. e p-sop8-4.4x4.85-1.27 0.1g mass[typ.] ? prsp0008de-c renesas code jeita package code previous code 1 l l
m62333p/fp, m62338p/fp preliminary r03ds0038ej0500 rev.5.00 page 9 of 9 jun 03, 2011 2. 1. dimensions "*1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. b p a 1 h e y 0.1 e 1.27 c 0 10 l 0.2 0.4 0.6 0.05 a 1.9 5.9 6.2 6.5 a 2 1.5 e 4.2 4.4 4.6 d 4.8 5.0 5.2 reference symbol dimension in millimeters min nom max 0.35 0.4 0.5 0.13 0.15 0.2 p-sop8-4.4x5-1.27 0.07g mass[typ.] 8p2s-a prsp0008da-a renesas code jeita package code previous code 1.12 1.42 detail f l a 1 a 2 f *1 *2 *3 85 4 1 index mark y b p e a c e h e d
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